The present invention relates to a reproducing device and reproducing method for a disk such as a CD-ROM in which coded data are recorded, and particularly to a device and method of reproducing an optical disk in which data are recorded in the constant linear velocity system.
Recently, as an example of a device for reproducing data recorded on an optical disk, there are a compact disk player (hereinafter, referred to as CD player), a CD-ROM drive device in which a compact disk (hereinafter, referred to as CD) is used a read-only memory, etc. As a CD-ROM drive device becomes popular, the request for providing a CD-ROM drive device with a reproducing function which enables fast access while attaining low-power consumption is growing.
Recording systems for a disk include the constant linear velocity system (hereinafter, referred to as CLV system) which is characterized in high-density recording, and the constant angular velocity system (hereinafter, referred to as CAV system) which is characterized in high-speed search. For example, Japanese Patent Unexamined Publication (Tokkai) No. Hei6-36289 discloses a method in which a disk wherein recording was performed by the CLV system is reproduced under CAV-rotation. Japanese Patent Unexamined Publication (Tokkai) No. Sho62-88170 discloses a method in which a disk wherein recording was performed by the CLV system is reproduced at a linear velocity higher than a specified linear velocity. In the former method, influences of the rotation settlement of a spindle servo can be eliminated, and the pickup-moving time is substantially equal to the access time. The latter is a system in which reproduction can be started even in a period when the CLV rotation settlement has not yet reached the final linear velocity. As the rotation number of a spindle motor is increased to a double speed or a quadruple speed, the effects of these systems are further recognized. For example, results of a technical study on the variable linear velocity reproduction system are reported in NIKKEI ELECTRONICS No. 628 (Feb. 13, 1995), pp. 111 to 119. In the report of NIKKEI ELECTRONICS, the term of variable velocity reproduction is used. In the following description, however, reproduction under the state where the linear velocity has not yet reached the final target is called the variable linear velocity reproduction system.
In a usual CD player or a CD-ROM device, the read clock signal is fixed, and the rotation of a disk is synchronized in phase with the read clock signal. Such a player or device is configured so that data which were once stored in a memory or the like by using the write clock signal synchronized with the regenerative clock signal are read out in synchronization with the read clock signal, thereby absorbing the time fluctuation.
By contrast, in a CD-ROM drive device, it is not particularly necessary to read out data by using a fixed clock signal. Therefore, such a device may be configured so as to read out data in accordance with rotation of a disk. The above-mentioned variable linear velocity reproduction system is a reproduction system which was developed in view of the above.
Hereinafter, a conventional CD-ROM drive device using the CLV system, and the variable linear velocity reproduction system exemplified by Japanese Patent Unexamined Publication (Tokkai) No. Hei3-36289 will be described.
FIG. 57 is a block diagram showing the configuration of a conventional CD-ROM drive device using the CLV system. The device comprises: a CD-ROM disk (hereinafter, referred to as CD) 1 wherein recording was performed by the CLV system; an optical pickup 5; a binarizing circuit 8 which converts a reproduced signal into a digital signal; an EFM (Eight to Fourteen Modulation code) demodulation circuit 10; a serial-parallel converting circuit 30; a write clock signal generating circuit 31; a PLL (Phase Locked Loop) circuit 9 which extracts a clock signal from a binary signal; a synchronization detecting circuit 11 which extracts a synchronizing signal recorded in each frame; a buffer RAM 13 which is used as a temporary memory for storing EFMxe2x80x94demodulated data and executing absorption of rotation jitter and error correction based on a CIRC (Cross Interleave Reed-Solomon Code); a parallel-serial converting circuit 32; a read clock signal generating circuit 33; a RAM write address generating circuit 34 which generates a write address for the buffer RAM 13; a RAM read address generating circuit 35 which generates a read address for the buffer RAM 13; a crystal oscillation circuit 36; a frequency divider 37; a CD-ROM decoder 22 which performs a CD-ROM decoding process; a CIRC decoder 21 which executes error correction based on a CIRC; a frequency comparison circuit 38 which compares the output of the PLL circuit 9 with that of the crystal oscillation circuit 36 and obtains a frequency difference; a phase comparison circuit 39 which compares the output of the REM write address generating circuit 34 with that of the BAM read address generating circuit and obtains a phase difference; a spindle control circuit 3 which controls a spindle motor by using results of the frequency comparison and the phase comparison; the spindle motor 2; and a traverse motor 7 which moves the optical pickup 5 in a radial direction.
Hereinafter, the operation of the device shown in FIG. 57 will be described.
The optical pickup 5 performs focus and trackingxe2x80x94processes on pit strings on the CD 1, and outputs a reproduced analog signal. The output is converted into a digital signal by way of the binarizing circuit 8. The digital signal is demodulated by the EFM demodulation circuit 10. Then, the clock signal is extracted by the PLL circuit 9, and the synchronizing signal recorded in each frame is detected by the synchronization detecting circuit 11. An address for the buffer RAM 13 is generated by using the synchronizing signal extracted by the synchronization detecting circuit 11. On the other hand, in a signal processing side, the output of the crystal oscillation circuit 36 is used as the reference clock signal. The read address is generated from the reference clock signal. The signal processing side is a portion (including the CIRC decoder 21) which executes the data processing subsequent to the buffer RAM 13. The buffer RAM 13 is used as a buffer for absorption of rotation jitter and error correction. In a compact disk player which is used for the purpose of audio, generally, such a buffer for absorbing rotation jitter is disposed in order to prevent rotation fluctuation due to rotation of a motor from being transmitted to a reproduced audio signal. The phase comparator 39 compares the phase difference between the clock signal written into the buffer RAM 13 and that read out therefrom, and the phase difference is used in the control of the spindle motor 2, thereby enabling the difference between the write and read addresses generated by rotation fluctuation to be canceled in a rotation control side.
FIG. 58 illustrates the memory management of the buffer RAM 13 of FIG. 57, in the form of a ring. The buffer RAM 13 is divided into an error correction region and a rotation jitter absorption region, and performs address generation and a ring buffer operation. Reproduced data are written into a clockwise direction. Similarly, the operation of reading out reproduced data is performed in a clockwise direction. Reproduced data are stored in a region extending from point C to point A in a clockwise direction. Therefore, the region extending from point A to point C is a spare space region. The spindle motor 2 is controlled so that the write address is settled down to point C where is the middle point of the rotation jitter absorption region. When the rotation jitter is operated in a direction along which the data transfer rate is increased, point C approaches point A in a counterclockwise direction. When the rotation jitter is operated in a direction along which the data transfer rate is reduced, point C approaches point B in a clockwise direction.
FIG. 59 is a block diagram showing the configuration of the variable linear velocity reproduction system which is formed with reference to the above-mentioned patent publication (Japanese Patent Unexamined Publication (Tokkai) No. Hei3-36289). This configuration is different from the circuit configuration shown in FIG. 57 in that the outputs of the PLL circuit 9 and the crystal oscillation circuit 36 are supplied to the spindle control circuit 3, and that a clock signal for signal processing generating circuit 40 to which the output of the PLL circuit 9 is supplied is additionally disposed and the output of the circuit is used in place of that of the crystal oscillation circuit 36 in FIG. 57. The clock signal for signal processing generating circuit 40 generates the reference clock signal from the clock signal extracted by the PLL circuit 9.
Hereinafter, the operation of the circuit of FIG. 59 will be described. The same components as those used in FIG. 57 operate in the same manner. In the circuit of FIG. 59, the read clock signal is generated in the clock signal for signal processing generating circuit 40, and the spindle control is performed on the basis of the frequency comparison with the crystal oscillation circuit 36. According to this configuration, even when the rotation settlement of the spindle motor requires a prolonged period of time or the linear velocity is different from the final target, reproduction of data can be started. The CD-ROM decoder 22 is usually provided with a temporary memory of 64 kilobytes or more, and configured so as to smoothly conduct the data transfer with a host computer. In the case of a disk device for a computer, such as a CD-ROM drive device, therefore, there are occasions when fluctuation of the transfer speed of a reproduced signal does not produce a serious problem. When such configuration is employed, data reproduction is enabled even when the linear velocity has not yet reached the target, with the result that the torque of the spindle motor 2 in the case where the motor is shifted to high-speed rotation can be reduced. Furthermore, the heat generation and low-power consumption of the motor can be realized by the reduction of the motor torque.
In the configuration of the variable linear velocity reproduction system such as shown in FIG. 59, however, the spindle control system performs only the frequency comparison, and has a problem in that the system involves fixed linear velocity deviation from the target linear velocity.
Even if the linear velocity deviation is allowed, the configuration has another problem in that, when failure of reproduction of data on the disk due to fingerprints, scratches, or the like occurs to cause the output of the PLL circuit 5 to fluctuate, differences of the write address and the read address are cumulated. When a disk of a low reproduction quality is to be reproduced for a long period, for example, this problem appears as a symptom of data reproduction failure in the unit of interleave which exceeds the range of an error generated by a scratch on the disk surface or the like.
FIG. 60 is a timing chart illustrating the problem. The format shown in the upper portion of FIG. 60 is a data format of 1 frame of a CD. The timing chart shown in the second stage is a regenerative clock signal required for processing the frame format of the CD in the unit of a channel bit. The clock signal is an ideal one in which 588 clock pulses appear in 1 frame. By contrast, a regenerative clock signal shown in the third state shows the case where a clock signal extraction failure period occurs at some midpoint. When the PLL circuit 9 is subjected to fluctuation due to fingerprints, scratches, or the like, a count error is produced as described above. By contrast, when the clock signal in the RAM address read side which is generated by the clock signal for signal processing generating circuit 40 is not caused to largely fluctuate, the count difference is cumulated as an error. In some case, the cumulative clock signal error is cumulated in the system as cumulation of differences of clock pulse numbers, and, in other cases, cumulated as a cumulative phase difference between the write and read signals for the buffer RAM 13. In some cases, even when a difference of clock pulse numbers and a phase difference do not occur in a fixed period, clock signal fluctuation or phase fluctuation may occur in a short period. Also in the cases, such fluctuation appears similarly as a symptom of data reproduction failure.
Furthermore, it is possible to realize the low-power consumption due to reduction of the motor torque. However, reduction of the motor torque causes a problem in that the time (the spin-up time) elapsed before the rotation number reaches a predetermined value and the read operation is enabled is prolonged.
Moreover, the reduction causes another problem in that deterioration of the reproduction quality owing to disturbance or the like occurs during the period when variable linear velocity reproduction is executed.
When the spin-up time is to be ensured without reducing the motor torque, there arises a problem in that heat generation and power consumption are increased.
In the execution of variable linear velocity reproduction, in the case where the gain of the spindle motor is simply reduced, the power consumption can be lowered by reducing the control current of the motor. In the case where the range of the reproducing speed which can be process by the signal processing system is narrow, however, there is a problem in that the time elapsed before the rotation number reaches the target and the read operation is enabled is prolonged and the access time becomes long.
FIG. 61 is a block diagram showing the configuration of another conventional CDROM drive device.
In FIG. 61, a spindle motor 2 which rotates a CD 1 by the CLV system is controlled by a spindle control circuit 3. A crystal oscillation circuit 4 generates a fixed clock signal which is used in the spindle control. An optical pickup 5 which reads out digital data recorded on the CD 1 is moved to a target position by a traverse motor 7 which is controlled by an access control circuit 6. A binarizing circuit 8 shapes the waveform of the output of the optical pickup 5 and digitizes the output. A regenerative clock signal extracting PLL circuit 9 extracts a regenerative clock signal from reproduced data which are the output of the binarizing circuit. An EFM demodulation circuit 10 demodulates the reproduced data by using the regenerative clock signal, and outputs the demodulated data. A synchronization detecting circuit 11 detects a synchronizing signal for signal processing and outputs a synchronization detection signal. A buffer write control circuit 12 generates a write clock signal (write clock signal) and a write address (write address) for storing the demodulated data into a buffer 13, from the synchronization detection signal and the regenerative clock signal.
A clock signal for signal processing generating PLL circuit 19 comprises a regenerative clock signal divider 17 which divides the frequency of the regenerative clock signal, a clock signal for signal processing divider 18 which divides the frequency of the clock signal for signal processing, a phase comparator 15, a filter 14, and a voltage controlled oscillator (hereinafter, referred to as VCO) 16 which generates the clock signal for signal processing. The oscillation frequency of the VCO 16 is determined by feeding back via the filter 14 the phase error of the phase comparator 15 which phase-compares a regenerative clock division signal that is the output of the regenerative clock signal divider 17 with a clock signal for signal processing division signal that is the output of the clock signal for signal processing divider 18.
A buffer read control circuit 20 generates, by using the clock signal for signal processing, a read clock signal (read clock signal) and a read address (read address) for reading out demodulated data stored in the buffer. A CIRC decoder 21 performs signal processing such as error correction on the read out demodulated data, and then outputs the data (hereinafter, the data are referred to as CD data). The CD-ROM decoder 22 takes out user data in the CD-ROM format from the CD data.
The whole operation of the thus configured CD-ROM drive device will now be described. First, when the CD-ROM drive device reproduces data at the standard speed, the spindle control circuit 3 controls the rotation number of the spindle motor 2 so that the linear velocity at the current reproduction position is about 1.3 m/s. This is performed by conducting the rotation control so that the regenerative clock signal extracted from the reproduced data is synchronized with the fixed clock signal generated by the crystal oscillation circuit 4 and the regenerative clock signal is 4.3218 MHz. The reproduced data are demodulated by the EFM demodulation circuit 10 by using the regenerative clock signal, and then stored as demodulated data into the buffer 13.
FIG. 62 shows the frame format of a CD and the signal timing. One frame of a CD is configured by a sequence of the synchronizing signal, a control signal, 12 bytes of data, 4 bytes of error correction parity, 12 bytes of data, and 4 bytes of error correction parity. In normal reproduction, 1 frame consists of 588 regenerative clock pulses.
The demodulated data which are demodulated by using the regenerative clock signal are converted into parallel signals in the unit of 1 byte, and then sequentially written into the buffer in accordance with the write clock signal which is output from the buffer write control circuit 12 and used for transfer in the unit of 1 byte, and the write address in the unit of a frame.
The read clock signal and the read address are generated from the clock signal for signal processing by the buffer read control circuit 20. In the case of music reproduction, for example, the clock signal for signal processing is subjected to 2-channel sampling at 16 bits/sample at the sampling frequency in which the recording rate of musical data of the CD is 44.1 KHz. Therefore, 1.4112 Mbits/sec. is attained. It is preferable to use an integer multiple of 1.4112 MHz as the clock signal for signal processing. In consideration of decoding of CIRC, etc., usually, a fixed clock signal of 8.4672 MHz which is six times. Consequently, the clock signal for signal processing for 1 frame consists of 1,152 clock pulses.
FIG. 63 is a diagram illustrating the operation of the buffer. The buffer 13 has a capacity of, for example, .+xe2x88x92.4 frames, and is configured so that a predetermined byte is stored at an address in the unit of a frame with using the synchronizing signal as the reference. With respect to the write address and the read address, the same addresses exist at positions which are shifted from each other by 4 frames. In the case where the write address and the read address coincide with each other, therefore, when demodulated data are written, Xxe2x80x94demodulated data which were written at the timing preceding by four frames before are read out.
The demodulated data read out from the buffer 13 are transferred to a memory for storing an amount of data which is required for decoding in the CIRC decoder 21, and subjected to error correction, etc. by using the clock signal for signal processing. The CD data are sent to the CD-ROM decoder 22 and reproduced as user data.
When the clock signal for signal processing is fixed as in the case of a CD player, a difference between the write address and the read address is produced in the case where disturbance causes the rotation of the disk to fluctuate and the reproducing speed of reproduced data is changed. In such a case, rotation fluctuation of 3 frames or less can be absorbed by the buffer 13. When a difference of 4 frames or more is caused by large rotation fluctuation or the like, however, the demodulated data stored in the buffer 13 become empty or full to overflow, with the result that the signal processing cannot be correctly performed.
To comply with this, in a prior art CD-ROM drive device, the regenerative clock signal divider 17 which divides the frequency of the regenerative clock signal is set to perform 147 divisions, and the clock signal for signal processing divider 18 which divides the frequency of the clock signal for signal processing is set to perform 288 divisions. A phase comparison is conducted, and the clock signal for signal processing is generated based on the error in the comparison. According to this configuration, in normal reproduction, the oscillation frequency of the VCO is 8.4672 MHz and equal to that of music data reproduction. When the rotation number of the spindle motor 2 is changed during reproduction by disturbance or the like and the cycle of the regenerative clock signal fluctuates, generally, the fluctuation has a low frequency. Therefore, the clock signal for signal processing can be sufficiently followed because of the properties of the clock signal for signal processing generating PLL circuit 19, and hence an overflow or the blank state in the buffer due to excessive reading of the demodulated data does not occur. This is described in, for example, Japanese Patent Unexamined Publication (Tokkai) No. Sho60-195781.
In the case where the thus configured CD-ROM drive device is used, when track access from the current reproduction position is performed in order to reproduce data recorded at a different position, reproduction is enabled even when the disk has not yet reached the predetermined rotation number even at the timing when the optical pickup reaches the target position, thereby realizing high-speed access. This is described in, for example, Japanese Patent Unexamined Publication (Tokkai) No. Hei6-36289.
In the prior art configuration shown in FIG. 61, however, when abnormality is produced in reproduced data because of a defect on the disk or the like, there may arise the case where the extraction of the regenerative clock signal is not satisfactorily performed and the frequency of the regenerative clock signal is disturbed. As a result, the relationship between the number of the regenerative clock signal and that of the clock signal for signal processing is broken, and hence an overflow or a blank state occurs in the buffer, thereby producing a problem in that data reproduction cannot be correctly performed.
When the disk has not yet reached the predetermined rotation number at the timing when the optical pickup reaches the target position as a result of the access operation, the response of the clock signal for signal processing generating PLL circuit 19 is slower than the extraction of the regenerative clock signal, and hence the generation of the clock signal for signal processing synchronized with the regenerative clock signal requires a prolonged period. Therefore, an overflow or a blank state occurs in the buffer 13, so that variations are produced in timings of starting reproduction.
Moreover, the device has further problems which lead to increase of the production cost, such as that, in order to generate the clock signal for signal processing, the clock signal for signal processing generating PLL circuit 19 consisting of the regenerative clock signal divider 17, the clock signal for signal processing divider 18, the phase comparator 15, the filter 14, and the VCO 16 is required and the circuit scale is increased.
These problems will be described in detail with reference to FIGS. 64 and 65. FIG. 64 is a chart illustrating the manner of settlement of the clock signal for signal processing in the case where a defect exists on the disk. When the division ratios of the regenerative clock signal divider 17 and the clock signal for signal processing divider 18 are set to be 147 and 288, respectively, the frequency-divided signals of the regenerative clock signal and the clock signal for signal processing have 4 pulses per 1 frame.
When a defect exists on the disk, reproduced data cannot be correctly detected. In accordance with the erroneous detection, therefore, also the frequency of the regenerative clock signal is abruptly shifted to an abnormal one, so that the cycle of the frequency-divided signal of the regenerative clock signal is changed. Because of the properties of the clock signal for signal processing generating PLL circuit 19, however, it is impossible to abruptly change the frequency of the clock signal for signal processing. Namely, the frequency is changed in such a manner that the clock signal for signal processing is gradually synchronized with the frequency-divided signal of the regenerative clock signal which has been shifted in phase. In the case where the extraction of the regenerative clock signal is not correctly performed because of a defect in an n-th frame and only 560 clock pulses of the regenerative clock signal are generated in the n-th frame, for example, the cycle of the frequency-divided signal of the regenerative clock signal is prolonged. However, the clock signal for signal processing generating PLL circuit cannot follow the abrupt phase change, and a signal of 1,152 clock pulses is generated in the n-th frame. When the phase synchronization is realized in the next (n+1)-th frame, the clock signal for signal processing in the (n+1)-th frame has about 1,097 clock pulses. In this case, since, the write address and the write clock signal for the buffer are generated with using the synchronization detection signal as the reference, the change to the next address is normally conducted by the synchronization detection signal even when some pulses of the regenerative clock signal lack. Since the read clock signal and the read address are generated in a synchronized manner, however, data of 1 frame cannot be transferred in the (n+1)-th frame and the transfer is prolonged to the (n+2)-th frame. This causes the writing timing and the reading timing in the buffer to be shifted from each other. This shift will be continued even when the situation in which. the regenerative clock signal is correctly extracted is again established. When a CD having a number of defects is reproduced, the shift may be further enhanced by each of the defects, and hence an overflow or a blank state in the buffer due to excessive reading of the demodulated data occurs. The lack of data owing to such defects can be corrected by error correction. When an overflow or a blank state occurs in the buffer, however, the writing may be performed at an address which has not been read out or the data of an address which has been already read out may be again read out, with the result that the CIRC decoder 21 cannot correctly decode data. In order to prevent an overflow or a blank state from occurring in the buffer, therefore, the buffer must have a sufficient capacity.
Next, variations of timings of starting reproduction during the access operation will be described with reference to FIG. 65. FIG. 65 is a chart illustrating the state of the clock signal for signal processing before and after the access operation.
First, the optical pickup 5 reproduces an inner peripheral position of the CD 1. The access operation is started at time t1. Before time t1, therefore, the rotation number of the CD 1 is high, the linear velocity has a predetermined value or remains constant, and both the regenerative clock signal and the clock signal for signal processing proceed at normal frequencies. During times t1 and t2, the traverse operation for moving to the target position is conducted so that the optical pickup 5 reaches the target position at time t2. During the period before the optical pickup 5 reaches the target position, since correct reproduced data cannot be detected, the extraction of the regenerative clock signal is aborted, and the frequency is held to the oscillation frequency obtained at t1. At time t2 when the optical pickup 5 reaches the target position, the rotation number of the CD 1 has not yet reached the predetermined one. This is caused by the fact that it is difficult to abruptly change the rotation of a disk because of problems in properties and heat generation of the spindle motor. Consequently, the linear velocity at time t2 is higher than the predetermined linear velocity. During the period after the optical pickup 5 reaches the target position and before time t3, the regenerative clock signal is promptly extracted by the regenerative clock signal for signal processing generating PLL circuit 19. However, the frequency of the clock signal for signal processing cannot be abruptly changed because of the properties of the clock signal for signal processing generating PLL circuit 19, and gradually approaches the frequency for a higher linear velocity. At time t4, the clock signal for signal processing is settled to the frequency corresponding to the linear velocity. The frequency shift occurring during this period causes the buffer 13 to repeat overflow. Since the timing of time t4 is varied depending on the position of the start of the traverse, the period of the traverse, etc., also the time when normal data reproduction is enabled is varied.
At time t4, the relationship between the write address and the read address is indefinite. Consequently, a defect on the CD 1 may immediately produce the problems of overflow, etc.
When the portion for extracting the regenerative clock signal in a prior art device is configured by a semiconductor LSI, the properties of the regenerative clock signal for signal processing generating PLL circuit are varied depending on the semiconductor process. As a result, there arises a problem in that correct data cannot be detected and the error rate of reproduced data is increased.
FIG. 66 is a block diagram showing the configuration of a further conventional CD-ROM drive device.
In FIG. 66, data are recorded on a CD 1 in a system in which the linear recording density is constant. An optical pickup 5 detects and reproduces the recorded signals on the CD 1 as analog waveforms. A binarizing circuit 8 binarizes the analog waveforms. A regenerative clock signal extracting PLL circuit 9 extracts a regenerative clock signal for reproducing data from the binarized signal, by means of a PLL (Phase Locked Loop). A synchronization detecting circuit 11 detects a frame synchronizing signal from the output of the binarizing means 8. When a disk of a constant linear recording density is rotated at a constant angular velocity, the frequencies of the regenerative clock signal and the frame synchronizing signal are lower as the optical pickup 5 is at a more inner peripheral side, and higher as the optical pickup is at a more outer peripheral side. Demodulation/correction 316 demodulates data from the output of the binarizing means 8 in synchronization with the frame synchronizing signal, and performs code error correction based on a CIRC (Cross Interleave Reed-Solomon Code). A CD-ROM decoder means 22 descrambles scrambled data of a CD-ROM output from the demodulation/correction means 316, subjects the descrambled data to error detection and correction as CD-ROM data, and outputs the data. Spindle motor means 2 rotates the CD 1. A spindle control circuit 3 compares the outputs of a crystal eschewal late circuit 36 as a reference clock signal generating means and the synchronization detecting circuit 11 with each other, and controls the spindle motor means 2 in a closed loop so that the linear velocity of the CD 1 is constant.
The operation of the thus configured CD-ROM drive device of the prior art example 3 in the track access will be described. It is assumed that the optical pickup 5 is first at a predetermined position and the CD 1 is rotated at a constant linear velocity. The optical pickup 5 is moved to a target position on the CD 1. During the movement of the optical pickup 5, the synchronization detecting means 11 cannot detect the frame synchronizing signal. When the rotation control of the CD 1 is to be performed simultaneously with the movement of the optical pickup 5, usually, the methods described below are used in the control of the spindle motor means 2.
Namely, such methods include the method in which signal components of the shortest cycle of modulated signals recorded on the CD 1 are extracted and the control is performed on the basis of the cycle, the method which is performed in response to compelled acceleration and deceleration commands in an open loop, and the method in which means for detecting the rotation number of the spindle motor means 2 is disposed and the control is performed in a closed loop (this is referred to as FG control system). Consequently, it is assumed that the spindle control circuit 3 is controlled by one of the above-described methods described. When the optical pickup 5 is moved to the target position, the regenerative clock signal and the frame synchronizing signal which have a frequency proportional to the linear velocity corresponding to the rotation number of the disk at this timing are output from the regenerative clock signal extracting PLL circuit 9 and the synchronization detecting circuit 11, respectively. The spindle control circuit 3 compares the reference clock signal from the crystal oscillation circuit 36 with the frame synchronizing signal from the synchronization detecting circuit 11, and controls the spindle motor means 2 so that the linear velocity of the CD 1 is coincident with the predetermined linear velocity. During this process, the demodulation/correction means 316 demodulates and corrects the data, but cannot obtain correct results. When the linear velocity of the CD 1 then reaches the predetermined linear velocity, the PLL of the regenerative clock signal extracting PLL circuit 9 is locked. At this timing, the demodulation/correction means 316 can correctly perform demodulation and correction of the data. The demodulated and corrected data are output to the CD-ROM decoder 22 at a constant transfer rate by using the reference clock signal from the crystal oscillation circuit 36, and reproduction of the CD-ROM data is started. The address information is detected from the reproduced CD-ROM data, whereby data can be read out from the target position on the CD 1.
However, the system described above has a problem in that data cannot be reproduced until the linear velocity of the CD 1 reaches the predetermined linear velocity and hence the access time is prolonged. In order to avoid the above-discussed problem, therefore, another system is recently attempted. In the system, the pull-in range (lock range) of the PLL of the regenerative clock signal extracting PLL circuit 9 is widened, and the output of the demodulation/correction means 316 is performed by using the regenerative clock signal of the regenerative clock signal extracting PLL circuit 9 in place of the reference clock signal, so as to be transferred to the CD-ROM decoder 22. This is described in, for example, Japanese Patent Unexamined Publication (Tokkai) No. Hei6-36289.
Conventionally, a CD-ROM drive device is configured by using the configuration of a reproduction device for a compact disk, as it is. In a reproduction. device for a compact disk, reproduction must be performed at a constant transfer rate in order to perform audio reproduction. In a CD-ROM drive device, however, data reproduction is not always required to be performed at a constant transfer rate. Therefore, the above-described system has been developed. In this system, i.e., the variable linear velocity reproduction system, the demodulation/correction means 316 performs demodulation and correction at the timing when the optical pickup 5 is moved to the target position. Even when the linear velocity of the CD 1 has not yet reached the predetermined linear velocity, the PLL of the clock signal extracting means 9 is locked, thereby allowing the demodulation/correction means 316 to correctly perform demodulation and correction at this timing. The demodulated and corrected data can be output to the CD-ROM decoding means 22 at a transfer rate depending on the linear velocity of the CD 1. According to this configuration, the access time can be largely shortened.
However, the access operation of a device of the variable linear velocity reproduction system such as the prior art example 3 described above involves the following problem. In access from the inner periphery to the outer periphery, for example, when the torque of the spindle motor means is so small that the rotation control of a disk is not sufficiently performed, the linear velocity of the disk becomes very high (the data reproducing speed is increased) and exceeds the limit of the adaptive ability of the data reproduction system, with the result that correct data cannot be reproduced. As a method which can prevent this problem from occurring, reported is an example (Japanese Patent Unexamined Publication (Tokkai) No. Hei6-119710) in which the frequency of the regenerative clock signal extracted by a PLL is measured, whereby the maximum reproducing speed (hereinafter, referred to as maximum linear velocity) is judged. In this case, even when the PLL is not perfectly locked, data reproduction may be erroneously started, thereby producing a problem in that the minimum error rate required in data reproduction cannot be ensured.
By contrast, when the rotation control of a disk is not sufficiently performed in access from the inner periphery to the outer periphery, the linear velocity of the disk is very low. In this case, a conventional system in which only the maximum linear velocity is supervised has a problem in that, in a kind of an application software for a CD-ROM, the linear velocity is lower than the minimum reproducing speed at which operation is enabled (hereinafter, the speed is referred to as minimum linear velocity), thereby presenting a danger that a normal operation cannot be expected.
It is an object of the invention to ensure the reproduction quality in the case where a disk recording performed by the CLV system is reproduced by the variable linear velocity reproduction system to realize both high-speed access and low power consumption.
The disk reproducing device of the invention comprises: phase comparison means for generating a virtual data read address from reference clock signal generating means, and performing phase comparison with a write address; and spindle control means for controlling rotation of a disk with reference to an output of frequency comparison means and an output of the phase comparison means. According to this configuration, a phase error can be fed back to a spindle motor, thereby preventing linear velocity deviation from occurring in a steady state.
The disk reproducing device of the invention comprises: phase comparison means for referring outputs of write address means and read address means, and performing phase comparison; spindle control means for controlling rotation of a disk with reference to an output of frequency comparison means and an output of the phase comparison means; and hold signal generating means for referring the output of the phase comparison means, and, when a phase error is not smaller than a constant value, holding an oscillation frequency of clock signal for signal processing generating means. According to this configuration, cumulative error between the read and write clock signals which is caused by fingerprints or scratches can be fed back to the control for a spindle motor, and hence it is possible to avoid a reproduction disable state due to the cumulative error.
In the disk reproducing method of the invention, a disk is rotated at a first linear velocity, the disk is then rotated at a second linear velocity which is higher than the first linear velocity, servo properties are automatically adjusted after the first linear velocity is attained, reproduction of a management region into which contents of a disk are written is started during a period when the first linear velocity is increased to the second linear velocity, and, after information of the management region is reproduced, reproduction of a data region is enabled. The method enables timing of starting data reproduction to be advanced.
The disk reproducing device of the invention comprises: spindle servo property switching means for using a plurality of closed loop properties for controlling a spindle motor, with switching over the properties; linear velocity supervisory means for supervising a linear velocity; and spindle control switching means for switching over properties of the spindle servo property switching means with reference to a judgement result of the linear velocity supervisory means. According to this configuration, a spindle control command which is one of disturbance factors in a period when the linear velocity is changed can be set to be small, thereby realizing stable data reproduction.
In the disk reproducing method of the invention, a function of performing a read-ahead process in which data are reproduced from data reproduction blocks is provided, the number of the data reproduction blocks being larger than a block number requested in one data reproduction request, a spindle motor is controlled with reference to a period when blocks corresponding to the data reproduction request are to be reproduced, and the control of the spindle motor is stopped with reference to a period when the read-ahead process in which no data reproduction request is issued is to be performed. According to this configuration, power consumption can be reduced by a degree larger than that of reduction of power consumption which is attained by reducing the motor torque.
The disk reproducing device of the invention comprises: spindle servo property switching means for using a plurality of closed loop properties for controlling a spindle motor, with switching over the properties; linear velocity supervisory means for supervising a linear velocity; and spindle control switching means for switching over properties of the spindle servo property switching means with reference to a judgement result of the linear velocity supervisory means. According to this configuration, the power consumption and heat generation of a spindle motor can be suppressed to a level as low as possible while high-speed access is performed, and data reading can be performed at a high speed. Namely, when the spindle is to be accelerated, the time constant of the servo is increased, and, when the spindle is to be decelerated, the time constant of the servo is reduced. As a result, the variation amount of the disk rotation is considerably reduced, and the power consumption and heat generation of the motor can be suppressed to a very low level as compared with the case of constant linear velocity reproduction. Simultaneously, in both acceleration and deceleration, the access time can be shortened. After the movement of a pickup is ended, the gain of the spindle servo property is made larger in acceleration, thereby allowing the velocity to reach more rapidly the target reproduction velocity. By contrast, in deceleration, the gain is reduced, so that data are transferred more rapidly. When the spindle control is turned OFF during the deceleration, it is possible to save the control current to be supplied to the motor. Therefore, the power consumption and heat generation can be suppressed to a level as low as possible. The judgement on acceleration and deceleration of the spindle motor can be correctly performed by comparing the rotational cycle of the disk.
In the disk reproducing device of the invention, in access to a target address, the gain of the spindle servo property is made smaller in a zone in which a spindle speed command is inverted, thereby reducing influences on the rotation number of the disk as much as possible. After the pickup position passes through the spindle command inversion zone, the gain of the spindle servo property is made larger so that the rotation number is rapidly directed to the target. This can suppress a waste change of rotation to a level as low as possible. As a result, needless rotation variation which is originally unnecessary can be suppressed, and waste energy consumption and heat generation can be prevented from occurring.
The disk rotation control method of the invention is a method in which cycle detecting means detects a rotational cycle of a disk, spindle command switching means allows spindle motor means to be used with switching over a plurality of command methods, and spindle control switching means instructs a switching method of the spindle command switching means. In the method, in access to a target address, upper and lower limits of the rotational cycle of the disk at which reproduction at a target address position is enabled are obtained, a target rotational cycle is determined, and, until an output of the cycle detecting means reaches the target rotational cycle, the maximum angular acceleration is supplied in an open loop to the spindle motor means, whereby a spindle is maximumly accelerated and decelerated until a target rotation number is attained. Therefore, at the same time as the start of the traverse movement, settlement to the target rotation number can be performed, and hence the rotation settlement can be performed for a short time. The rotational cycle of the disk immediately before access is compared with the target rotational cycle. If the rotational cycle has already reached the target when access is accepted, the gain of the spindle control is made smaller or free run is performed so that the rotational cycle is maintained as far as possible. This can suppress the energy consumed by the spindle motor to the minimum level while enabling high-speed access.
In the disk rotation control method of the invention, upper and lower limits of the rotational cycle of a disk at which reproduction at a target address position is enabled are obtained, comparison with the rotational cycle of the disk immediately before access is performed, a target rotational cycle is determined, and the target rotational cycle is set to rotational cycle control means. Therefore, the rotational cycle can reach for a shortest period a rotational cycle at which variable linear velocity reproduction is enabled. If, when access is accepted, the rotational cycle has already reached the target, the rotational cycle can be maintained. Therefore, the energy consumed by a spindle motor can be suppressed to the minimum level while high-speed access is enabled. During a period other than that when the access command is executed, the focus and tracking control of an optical pickup is turned OFF. Consequently, heat generation and energy consumption in an optical pickup mechanism can be reduced to a minimum required level.
In the disk reproducing device of the invention, in access to a target address, upper and lower limits of the rotational cycle of a disk at which reproduction at a target address position is enabled are obtained, comparison with the rotational cycle of the disk immediately before access is performed, and, if, when access is accepted, the rotational cycle has already reached the target, the gain of the spindle control is made smaller or free run is performed so that the rotational cycle is maintained as far as possible. This can suppress the energy consumed by a spindle motor to the minimum level. If the rotational cycle is outside the target range, the gain of the spindle control is made larger, whereby the rotation of the spindle can be controlled more promptly into the target range, so that high-speed access is realized.
The disk reproducing device of the invention comprises: regenerative clock signal generating means for extracting a regenerative clock signal from reproduced data; demodulation means for demodulating the reproduced data in accordance with the regenerative clock signal, and outputting demodulated data; synchronizing signal detecting means for detecting a synchronizing signal for signal processing from the reproduced data, and outputting a synchronization detection signal; data storage means for sequentially storing the demodulated data; clock signal for signal processing generating means for generating clock signals of a predetermined number for signal processing for each synchronization detection signal; and signal processing means for reading out demodulated data stored In the data storage means, in accordance with the clock signals for signal processing, and performing signal processing such as error correction. According to this configuration, even when the regenerative clock signal cannot be normally extracted in reproduction because of a defect on the disk, it is possible to eliminate an overflow and a blank state in a buffer. Even when a predetermined reproducing speed has not yet attained after access is performed, the clock signal for signal processing can be promptly generated, and hence high-speed access is enabled. Since a PLL circuit is not used, the circuit scale can be reduced. This can lower the cost.
The disk reproducing device of the invention comprises: regenerative clock signal generating means for extracting a regenerative clock signal from reproduced data; demodulation means for demodulating the reproduced data in accordance with the regenerative clock signal, and outputting demodulated data; synchronizing signal detecting means for detecting a synchronizing signal for signal processing from the reproduced data, and outputting a synchronization detection signal; data storage means for sequentially storing the demodulated data; clock signal for signal processing generating means for generating a clock signal for signal processing; signal processing means for reading out demodulated data stored in the data storage means, in accordance with the clock signal for signal processing, and performing signal processing such as error correction; dividing means for dividing a frequency of the clock signal for signal processing by a predetermined number, and outputting a frequency-divided signal; and signal cycle comparison means for phase-comparing the synchronization detection signal with the frequency-divided signal, and outputting a comparison error signal, the clock signal for signal processing generating means generating the clock signal for signal processing on the basis of the comparison error signal. In this way, even when the regenerative clock signal cannot be normally extracted in reproduction because of a defect on the disk, it is possible to eliminate an overflow and a blank state in a buffer.
The disk reproducing device of the invention comprises: regenerative clock signal generating means for extracting a regenerative clock signal from reproduced data; demodulation means for demodulating the reproduced data in accordance with the regenerative clock signal, and outputting demodulated data; synchronizing signal detecting means for detecting a synchronizing signal for signal processing from the reproduced data, and outputting a synchronization detection signal; data storage means for sequentially storing the demodulated data; write address generating means for generating a write address for the data storage means from the synchronization detection signal clock signal for signal processing generating means for generating a clock signal for signal processing; signal processing means for performing signal processing such as error correction on demodulated data stored in the data storage means, in accordance with the clock signal for signal processing; dividing means for dividing a frequency of the clock signal for signal processing by a predetermined number, and outputting a frequency-divided, signal; read address generating means for generating a read address for reading out demodulated data from the data storage means, by using the frequency-divided signal; and address comparison means for comparing the write address with the read address, and outputting an address comparison error signal, the clock signal for signal processing generating means generating the clock signal for signal processing on the basis of the address comparison error signal. In this way, even when the regenerative clock signal cannot be normally extracted in reproduction because of a defect on the disk, it is possible to eliminate an overflow and a blank state in a buffer. When it becomes possible to normally extract the regenerative clock signal, the write and read addresses of the buffer have the same value, thereby producing an advantage that an optimum buffer margin can be always maintained.
The disk reproducing device of the invention comprises: regenerative clock signal generating means for extracting a regenerative clock signal from reproduced data; demodulation means for demodulating the reproduced data in accordance with the regenerative clock signal, and outputting demodulated data; synchronizing signal detecting means for detecting a synchronizing signal for signal processing from the reproduced data, and outputting a synchronization detection signal; data storage means for sequentially storing the demodulated data; write address generating means for generating a write address for the data storage means from the reproduced data; clock signal for signal processing generating means for generating a clock signal for signal processing; signal processing means for performing signal processing such as error correction on demodulated data stored in the data storage means, in accordance with the clock signal for signal processing; dividing means for dividing a frequency of the clock signal for signal processing by a predetermined number, and outputting a frequency-divided signal; read address generating means for generating a read address for reading out demodulated data from the data storage means, in accordance with the frequency-divided signal; address comparison means for comparing the write address with the read address, and outputting an address comparison error signal; and address reset means for simultaneously setting the write address and the read address to a predetermined value, the clock signal for signal processing generating means generating the clock signal for signal processing on the basis of the address comparison error signal. In this way, even when the regenerative clock signal cannot be normally extracted in reproduction because of a defect on the disk, it is possible to eliminate an overflow and a blank state in a buffer. When it becomes possible to normally extract the regenerative clock signal, the write and read addresses of the buffer have the same value, thereby producing an advantage that an optimum buffer margin can be always maintained. Irrespective of an overflow and a blank state in the buffer at the timing of starting data reproduction after access, correct reproduction timing can be realized. Therefore, variations of timings of starting reproduction can be reduced and high-speed access is enabled.
The regenerative clock signal generating device of the invention comprises; a phase comparator; a phase/voltage converter; a voltage controlled oscillator; and reference signal generating means for generating two signals having a predetermined phase difference. The two output signals of the reference signal generating means are selected, and properties of the phase/voltage converter are changed in accordance with the output voltage of the phase/voltage converter. According to this configuration, variations of properties of a charge pump can be adjusted at startup, and influences of variations of properties due to the semiconductor process can be eliminated.
In the disk reproducing device of the invention, it is verified by using a synchronizing signal that the regenerative clock signal is normally extracted, and thereafter the maximum linear velocity at which reproduction is enabled is supervised. Therefore, data reproduction is prevented from being erroneously started when a PLL is not perfectly locked, and stable data reproduction can be performed. Consequently, the minimum error rate required in data reproduction can be ensured. Furthermore, the minimum linear velocity can be set to a target at which reproduction is enabled, and supervised. Therefore, it is possible to ensure the range of the minimum linear velocity where a normal operation of an application software is enabled.
When the maximum linear velocity which is to be set as the target is changed in accordance with the data format of the disk, the power source voltage, the ambient temperature, or results of code error correction of the reproduced signal, a margin for the maximum linear velocity required for stable operation can be made smaller. As a result, access of a higher speed can be performed.
The novel features of the invention are particularly set forth in the appended claims. Both the configuration and contents of the invention will be understood and appreciated more fully together with other objects and features from the following detailed description which will be understood in cooperation with the drawings.